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Ordering number : EN*5127A
CMOS LSI
LC78836M
Digital Audio 16-bit D/A Converter with On-Chip Digital Filters
Preliminary Overview
The LC78836M is a 16-bit CMOS D/A converter that includes 8x oversampling filters on chip. It is pin compatible with the LC78835M and LC78835KM. * Single 5 V power supply * Low-voltage operation (3 V) also possible * Si-gate CMOS process for low power dissipation
Package Dimension
unit: mm 3155-MFP24
[LC78836M]
Functions and Features
Digital Filter Block * 8x oversampling filters: Three FIR filter stages (33rdorder, 13th-order, and ninth-order filters) * De-emphasis filter: Support for 32 kHz, 44.1 kHz, and 48 kHz Fs frequencies * Soft muting * Noise shaper * Supports double-speed operation D/A Converter Block * 16-bit dynamic level shifting D/A conversion * Two D/A converter channels on a single chip (synchronous outputs) * On-chip output operational amplifiers * System clock: Supports 384 fs, 392 fs, 448 fs, and 512 fs clocks
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD max VIN VOUT Topr Tstg Conditions
SANYO: MFP24
Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 to +75 -40 to +125
Unit V V V C C
Allowable Operating Ranges
Parameter Supply voltage Reference voltage (high) Reference voltage (low) Operating temperature Symbol VDD VrefH VrefL Topr Conditions min 3.0 VDD - 0.3 0 -30 typ 5.0 max 5.5 VDD 0.3 +75 Unit V V V C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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103098HA(OT)/63095HA (OT) No. 5127-1/12
LC78836M DC Characteristics at Ta = -30 to +75C, VDD = 3.0 to 5.5 V, VSS = 0 V
Parameter Input high level voltage (1) Input low level voltage (1) Input high level voltage (2) Input low level voltage (2) Output high level voltage Output low level voltage Input leakage current Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL IL Conditions Pins 3, 4, 5, 6, 7, 13, 14, 15, 16, 17, and 18 Pins 3, 4, 5, 6, 7, 13, 14, 15, 16, 17, and 18 Pin 11 Pin 11 Pin 9: IOH = -3 mA Pin 9: IOL = 3 mA Pins 3, 4, 5, 6, 7, 11, 13, 14, 15, 16, 17, and 18: VI = VSS, VDD -25 2.4 0.4 +25 0.7 VDD 0.3 VDD min 2.2 0.8 typ max Unit V V V V V V A
AC Characteristics at Ta = -30 to +75C, VDD = 3.0 to 5.5 V, VSS = 0 V
Parameter Oscillator frequency Clock pulse width Clock pulse period BCLK pulse width BCLK pulse period Data setup time Data hold time LRCK setup time LRCK hold time Symbol fX tCW tCY tBCW tBCY tDS tDH tLRS tLRH Conditions The XIN pin when a crystal oscillator is used When an external clock is input to the XIN pin When an external clock is input to the XIN pin min 1.0 18 40 60 120 40 40 40 40 1000 typ max 25 Unit MHz ns ns ns ns ns ns ns ns
Audio Input Waveforms
No. 5127-2/12
LC78836M Electrical Characteristics (1) at Ta = 25C, AVDD = DVDD = VrefH = 5.0 V, AGND = DGND = VrefL = 0 V unless otherwise specified
Parameter DAC resolution Total harmonic distortion Dynamic range Crosstalk Signal-to-noise ratio Full-scale output voltage Power dissipation Output load resistance Symbol RES THD DR CT S/N VFS Pd RL *2 Pins 21 and 23 5 For f = 1 kHz, 0 dB*1 For f = 1 kHz, -60 dB For f = 1 kHz, 0 dB JIS-A 96 2.8 100 3.0 90 3.2 135 92 94 -85 Conditions min typ 16 0.08 max Unit bits % dB dB dB Vp-p mW k
Note: 1. 0 dB means full scale. 2. XIN amplitude (pin 11): 1.5 to 3.5 V, fX = 16.9344 MHz The test circuit should be based on the sample application circuit.
Electrical Characteristics (2) at Ta = 25C, AVDD = DVDD = VrefH = 3.0 V, AGND = DGND = VrefL = 0 V unless otherwise specified
Parameter DAC resolution Total harmonic distortion Dynamic range Crosstalk Signal-to-noise ratio Full-scale output voltage Power dissipation Output load resistance Symbol RES THD DR CT S/N VFS Pd RL *2 Pins 21 and 23 30 For f = 1 kHz, 0 dB*1 For f = 1 kHz, -60 dB For f = 1 kHz, 0 dB JIS-A 94 1.65 98 1.8 20 1.95 30 90 92 -85 Conditions min typ 16 0.10 max Unit bits % dB dB dB Vp-p mW k
Note: 1. 0 dB means full scale. 2. XIN amplitude (pin 11): 0.9 to 2.1 V, fX = 16.9344 MHz The test circuit should be based on the sample application circuit.
Block Diagram
No. 5127-3/12
LC78836M Pin Assignment
Top view
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol REFH VrefH MUTE D/N BCLK DATA LRCK DVDD CKOUT XOUT XIN DGND INITB EMP High-level reference voltage Normally connected through a capacitor to AGND. High-level reference voltage input Muting signal input The soft muting function is turned on by a high input. Standard/double-speed mode switching input Double-speed operation when high, standard when low. Bit clock input Digital audio data input Input is in a twos-complement MSB-first format. LR clock input CH1 is input when this pin is high, CH2 when low. Digital system power supply Clock output In 392 fs mode: outputs a 196 fs clock In other modes: outputs a clock with the XIN frequency Crystal oscillator output (system clock output) Crystal oscillator input (system clock input) Digital system ground Initialization signal input The LSI is initialized when this pin is set low. De-emphasis filter on/off switching The filter is turned on when this pin is set high, off when set low. De-emphasis filter mode (32, 44.1, or 48 kHz) selection 15 FS1 FS1 FS2 16 FS2 fs System clock selection 17 CKSL1 CKSL1 L L 18 CKSL2 H H 19 20 21 22 23 24 VrefL REFL CH2OUT AGND CH1OUT AVDD CKSL2 L H L H System clock 384 fs 392 fs 448 fs 512 fs L L 44.1 kHz H L H H 32 kHz L H 48 kHz Function
Low-level reference voltage input Low-level reference voltage Normally connected through a capacitor to AGND. CH2 analog output Analog system ground CH1 analog output Analog system power supply
No. 5127-4/12
LC78836M Operating Description 1. Digital Filters The LC78836M performs the following calculations.
* Oversampling The oversampling circuit consists of 2x interpolation filters (implemented as FIR filters) connected in series. In standard-speed operation, the circuit implements 8x oversampling by connecting three stages of FIR filters (33rd,13th, and ninth orders) in series. In double speed operation, the circuit implements 4x oversampling by connecting two stages of FIR filters (33rd and ninth orders) in series. See page 9 for the filter characteristics. * De-emphasis The LC78836M implements digital de-emphasis with a first-order IIR filter. The filter coefficients correspond to sampling frequencies (fs) of 32, 44.1, and 48 kHz. (The frequencies are doubled in double-speed operation.) See page 10 for the filter characteristics when de-emphasis is on. -- De-emphasis on/off switching De-emphasis on: EMP = high De-emphasis off: EMP = low -- Filter coefficient selection
FS1 FS2 fs L L 44.1 kHz H L H H 32 kHz L H 48 kHz
No. 5127-5/12
LC78836M * Soft muting Soft muting is implemented using the on-chip digital attenuator. The attenuator attenuation is given by the following formula. 20 Log (ATT/64) dB Here, ATT is an integer between 0 and 64 inclusive. However, the attenuation is - when ATT = 0. When the MUTE pin is set high, the ATT value is reduced one level at a time towards zero, and the attenuation changes, moving towards -. When the MUTE pin is set low, the ATT value is increased one level at a time towards 64, and the attenuation changes, moving towards 0 dB. The time required for the soft mute function to complete is about 1024/fs.
* Noise shaper The LC78836M uses a first-order noise shaper to reduce re-quantization noise in the output of the DF calculations. * Double-speed support The LC78836M supports double-speed CD playback when the D/N pin is set high. In this mode, the BCLK, LRCK, and DATA inputs should be input with twice the frequencies they have in standard-speed mode. Note that the system clock (the XIN pin clock) has the same frequency as it does in standard-speed mode. The LC78836M supports double-speed operation when the system clock is a 384 fs or 512 fs clock, but does not support this mode for 392 fs and 448 fs clocks. Since the LC78836M enters test mode for these settings, they should not be used. Standard-speed mode: D/N pin = low Double-speed mode: D/N pin = high 2. Initialization The LC78836M must be initialized when power is first applied or when the system clock is switched. Initialization is executed by setting the INITB pin low. While that pin is low, after the power supply voltage stabilizes, input the XIN, BCLK, and LRCK signals, and wait at least one LRCK period, as shown in the figure below. When INITB is low, all 16 bits of the digital filter outputs will be zeros, and the D/A converter outputs (CH1OUT and CH2OUT) will be analog 0 (a potential essentially equal to (VREFH + VREFL)/2).
No. 5127-6/12
LC78836M 3. System Clock The LC78836M supports four system clocks: 384 fs, 392 fs, 448 fs, and 512 fs. The CKSL1 and CKSL2 pins select the clock used.
CKSL1 L L H H CKSL2 L H L H System clock 384 fs 392 fs 448 fs 512 fs
* CKOUT pin For a 392 fs clock: Outputs a 196 fs clock (system clock/2) All other clocks: Outputs the system clock
4. Digital Audio Data Input The digital audio data is a 16-bit serial signal in an msb-first twos complement format. The 16-bit serial data is input from the DATA pin to an internal register on the rising edge of BCLK, and is latched on the next LRCK rising or falling edge.
No. 5127-7/12
LC78836M 5. D/A Converter Block The LC78836M incorporates an independent 16-bit D/A converter and an operational amplifier for signal output for each channel (CH1 and CH2). It adopts a dynamic level shifting conversion technique that uses a resistor-string D/A converter, a PWM (pulse width modulation) D/A converter, and a level shifting D/A converter. (See figure.)
* Resistor-string D/A converter This is an 8-bit D/A converter in which a total of 256 (= 28) unit-resistance resistors are connected in series and the potential applied to the ends of that resistor string is voltage divided into 256 equal intervals. Of these resistordivided potentials, two adjacent potentials, V1 and V2, are selected by a switching circuit according to the value of the upper 8 bits of the data. These two potentials are output to the PWM D/A converter. Note that these potentials are related as follows: V2 - V1 = (VH - VL)/256 * PWM D/A converter This is a 4-bit D/A converter that divides (by 16) the interval between the two potentials, V1 and V2, output by the resistor-string D/A converter. This circuit outputs one or the other of the V1 and V2 potentials from the CH1OUT (or CH2OUT) pin according to the value of the middle 4 bits of the data (D7 to D4).
No. 5127-8/12
LC78836M * Level shifting D/A converter This 4-bit D/A converter is implemented by connecting the variable resistors VRH and VRL in series at the ends of the resistor-string D/A converter resistors. The values of the VRH and VRL variable resistors are modified according to the value of the low-order 4 bits of the data (D3 to D0) as follows: -- The value of VRH + VRL is held fixed regardless of the value of the data. -- The values of VRH and VRL are changed in R/256 unit steps (where R is the value of the resistor-string D/A converter unit resistors) over the range zero to 15*R/256. This causes the resistor-string D/A converter V1 and V2 outputs to change in V/256 steps (where V = (VH -VL)/256) over the range 0 to 63 x V/256 according to the value of the lower 4 bits of the data. * VrefH/L and REFH/L pins The VrefH/L pins, which provide a reference voltage to the resistor string, are normally set to VrefH = AVDD and VrefL = AGND. Note that capacitors (about 10 F) should be connected between REFH and AGND and between REFL and AGND. When VrefH is 5.0 V and VrefL is 0 V, the LC78836M outputs its maximum output amplitude as the range 0.5 V (minimum) to 3.5 V (maximum) (3.0 Vp-p) for 0 dB playback according to the built-in RH and RL resistors. Filter Characteristics (logical values) Standard speed: 8x oversampling Double speed: 4x oversampling Ripple: Less than 0.1 dB Attenuation: -40 dB or lower Standard speed (de-emphasis off)
Double speed (de-emphasis off)
(fs*=2 x fs) No. 5127-9/12
LC78836M De-Emphasis ON Transient Bandwidth Characteristics * Standard Speed * Double Speed
Sample Application Circuit
Note: 1. In the diagram, DVDD and DGND are for the digital system, and AVDD and AGND are for the analog system. DGND and AGND must be connected to the digital system and analog system grounds, respectively. 2. A low-impedance high-stability power supply (equivalent to a commercial three-terminal regulator) must be used for AVDD and VrefH. 3. Since latchup can occur if there is a discrepancy in the pin 8 (DVDD) and pin 24 (AVDD) power supply voltage application timing, application circuits should be designed so that the pin 8 and pin 24 power supply voltages are applied at the same time. 4. Provide the XIN pin clock input quickly after power is applied. The IC may be destroyed if the XIN pin is held fixed at either the high or low level when power is applied.
No. 5127-10/12
LC78836M Power Supply Application Timing 1. The analog power supply (AVDD) and the digital power supply (DVDD) must be turned on at the same time and must be turned off at the same time. 2. If discrepancies in the analog and digital power supply timings cannot be avoided, the timings must fulfill the following conditions. * The difference between times when the power supplies rise must be 3 ms or shorter. (See Figure 1) * If the time difference is greater than 3 ms, then the power supply that rises (falls) first must have a rise time (fall time) of 5 ms or longer, and the time difference must be less than 50 ms. (See Figure 2)
Figure 1
Figure 2
No. 5127-11/12
LC78836M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject to change without notice. PS No. 5127-12/12

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